A Real-Time Stereo Matching Hardware Architecture Based on the AD-Census

In this paper, we propose a new stereo matching hardware architecture based on the ADCensus stereo matching algorithm that produces accurate disparity map. The proposed stereo matching hardware architecture is fully pipelined and processes images with disparity level parallelism in real time. Also, it uses modulo memory addressing methods for reducing the size of memory and the usage of hardware resource. The proposed architecture is perfectly synchronized with the input camera clock for real-time performance. Its maximum clock frequency is 197 MHz when it is implemented in an FPGA device.